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10-bit, 210 msps txdac ? d/a converter ad9740 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features high performance member of pin-compatible txdac product family excellent spurious-free dynamic range performance snr @ 5 mhz output, 125 msps: 65 db twos complement or straight binary data format differential current outputs: 2 ma to 20 ma power dissipation: 135 mw @ 3.3 v power-down mode: 15 mw @ 3.3 v on-chip 1.2 v reference cmos-compatible digital interface 28-lead soic, 28-lead tssop, and 32-lead lfcsp packages edge-triggered latches applications wideband communication transmit channel direct if base stations wireless local loops digital radio links direct digital synthesis (dds) instrumentation functional block diagram 1.2v ref reflo 3.3v r set 0.1 f clock sleep refio fs adj dvdd dcom clock digital data inputs (db9?db0) 150pf 3.3v avdd acom ad9740 current source array iouta ioutb mode lsb switches segmented switches latches 02911-001 figure 1. general description the ad9740 1 is a 10-bit resolution, wideband, third generation member of the txdac series of high performance, low power cmos digital-to-analog converters (dacs). the txdac family, consisting of pin-compatible 8-, 10-, 12-, and 14-bit dacs, is specifically optimized for the transmit signal path of communication systems. all of the devices share the same interface options, small outline package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost. the ad9740 offers exceptional ac and dc performance while supporting update rates up to 210 msps. the ad9740s low power dissipation makes it well suited for portable and low power applications. its power dissipation can be further reduced to 60 mw with a slight degradation in performance by lowering the full-scale current output. in addition, a power-down mode reduces the standby power dissipation to approximately 15 mw. a segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. edge-triggered input latches and a 1.2 v temperature-compensated band gap reference have been integrated to provide a complete monolithic dac solution. the digital inputs support 3 v cmos logic families. product highlights 1. the ad9740 is the 10-bit member of the pin-compatible txdac family, which offers excellent inl and dnl performance. 2. data input supports twos complement or straight binary data coding. 3. high speed, single-ended cmos clock input supports 210 msps conversion rate. 4. low power: complete cmos dac function operates on 135 mw from a 2.7 v to 3.6 v single supply. the dac full- scale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods. 5. on-chip voltage reference: the ad9740 includes a 1.2 v temperature-compensated band gap voltage reference. 6. industry-standard 28-lead soic, 28-lead tssop, and 32- lead lfcsp packages. 1 protected by u.s. patent numbers 5568145, 5689257, and 5703519.
ad9740 rev. b | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 3 specifications ..................................................................................... 4 dc specifications ......................................................................... 4 dynamic specifications ............................................................... 5 digital specifications ................................................................... 6 absolute maximum ratings ............................................................ 7 thermal characteristics .............................................................. 7 esd caution .................................................................................. 7 pin configurations and function descriptions ........................... 8 ter mi nolo g y ...................................................................................... 9 typical performance characteristics ........................................... 10 functional description .................................................................. 13 reference operation .................................................................. 13 reference control amplifier .................................................... 14 dac transfer function ............................................................. 14 analog outputs .......................................................................... 14 digital inputs .............................................................................. 15 clock input .................................................................................. 15 dac timing ................................................................................ 16 power dissipation ....................................................................... 16 applying the ad9740 ................................................................ 17 differential coupling using a transformer ............................... 17 differential coupling using an op amp ................................ 18 single-ended, unbuffered voltage output ............................. 18 single-ended, buffered voltage output configuration ........ 18 power and grounding considerations, power supply rejection ...................................................................................... 19 evaluation board ............................................................................ 20 general description ................................................................... 20 outline dimensions ....................................................................... 30 ordering guide .......................................................................... 31
ad9740 rev. b | page 3 of 32 revision history 12/05rev. a to rev. b updated format.................................................................. universal changes to general description and product highlights...........1 changes to table 1 ............................................................................4 changes to table 2 ............................................................................5 changes to table 5 ............................................................................8 changes to figure 6.........................................................................10 inserted figure 11; renumbered sequentially ............................10 changes to figure 12, figure 13, figure 14, and figure 15 .......11 changes to functional description and reference operation sections..........................................................................13 inserted figure 23; renumbered sequentially ............................13 changes to dac transfer function section and figure 25 ......14 changes to digital inputs section.................................................15 changes to figure 30 and figure 31 .............................................17 updated outline dimensions........................................................30 changes to ordering guide...........................................................31 5/03rev. 0 to rev. a added 32-lead lfcsp package ....................................... universal edits to features ................................................................................1 edits to product highlights .............................................................1 edits to dc specifications ...............................................................2 edits to dynamic specifications .....................................................3 edits to digital specifications..........................................................4 edits to absolute maximum ratings..............................................5 edits to thermal characteristics ....................................................5 edits to ordering guide...................................................................5 edits to pin configuration...............................................................6 edits to pin function descriptions ................................................6 edits to figure 2 ................................................................................7 replaced tpcs 1, 4, 7, and 8............................................................8 edits to figure 3 ..............................................................................10 edits to functional description section ......................................10 edits to digital inputs section.......................................................12 added clock input section............................................................12 added figure 7 ................................................................................12 edits to dac timing section........................................................12 edits to sleep mode operation section .......................................13 edits to power dissipation section...............................................13 renumbered figures 8 to 26..........................................................13 added figure 11 ..............................................................................13 added figures 27 to 35...................................................................21 updated outline dimensions........................................................26 5/02revision 0: initial version
ad9740 rev. b | page 4 of 32 specifications dc specifications t min to t max , avdd = 3.3 v, dvdd = 3.3 v, clkvdd = 3.3 v, i outfs = 20 ma, unless otherwise noted. table 1. parameter min typ max unit resolution 10 bits dc accuracy 1 integral linearity error (inl) ?0.7 0.15 +0.7 lsb differential nonlinearity (dnl) ?0.5 0.12 +0.5 lsb analog output offset error ?0.02 +0.02 % of fsr gain error (without internal reference) ?2 0.1 +2 % of fsr gain error (with internal reference) ?2 0.1 +2 % of fsr full-scale output current 2 2 20 ma output compliance range ?1 +1.25 v output resistance 100 k output capacitance 5 pf reference output reference voltage 1.14 1.20 1.26 v reference output current 3 100 na reference input input compliance range 0.1 1.25 v reference input resistance (external reference) 7 k small signal bandwidth 0.5 mhz temperature coefficients offset drift 0 ppm of fsr/c gain drift (without internal reference) 50 ppm of fsr/c gain drift (with internal reference) 100 ppm of fsr/c reference voltage drift 50 ppm/c power supply supply voltages avdd 2.7 3.3 3.6 v dvdd 2.7 3.3 3.6 v clkvdd 2.7 3.3 3.6 v analog supply current (i avdd ) 33 36 ma digital supply current (i dvdd ) 4 8 9 ma clock supply current (i clkvdd ) 5 6 ma supply current sleep mode (i avdd ) 5 6 ma power dissipation 4 135 145 mw power dissipation 5 145 mw power supply rejection ratioavdd 6 ?1 +1 % of fsr/v power supply rejection ratiodvdd 6 ?0.04 +0.04 % of fsr/v operating range ?40 +85 c 1 measured at iouta, dr iving a virtual ground. 2 nominal full-scale current, i outfs , is 32 times the i ref current. 3 an external buffer amplifier with input bias current <100 na should be used to drive any external load. 4 measured at f clock = 25 msps and f out = 1 mhz. 5 measured as unbuffered voltage output with i outfs = 20 ma, 50 r load at iouta and ioutb, f clock = 100 msps, and f out = 40 mhz. 6 5% power supply variation.
ad9740 rev. b | page 5 of 32 dynamic specifications t min to t max , avdd = 3.3 v, dvdd = 3.3 v, clkvdd = 3.3 v, i outfs = 20 ma, differential transformer coupled output, 50 doubly terminated, unless otherwise noted. table 2. parameter min typ max unit dynamic performance maximum output update rate (f clock ) 210 msps output settling time (t st ) (to 0.1%) 1 11 ns output propagation delay (t pd ) 1 ns glitch impulse 5 pv-s output rise time (10% to 90%) 1 2.5 ns output fall time (10% to 90%) 1 2.5 ns output noise (i outfs = 20 ma) 2 50 pa/hz output noise (i outfs = 2 ma) 2 30 pa/hz noise spectral density 3 ?143 dbm/hz ac linearity spurious-free dynamic range to nyquist f clock = 25 msps; f out = 1.00 mhz 0 dbfs output 71 79 dbc ?6 dbfs output 75 dbc ?12 dbfs output 67 dbc ?18 dbfs output 61 dbc f clock = 65 msps; f out = 1.00 mhz 84 dbc f clock = 65 msps; f out = 2.51 mhz 80 dbc f clock = 65 msps; f out = 10 mhz 78 dbc f clock = 65 msps; f out = 15 mhz 76 dbc f clock = 65 msps; f out = 25 mhz 75 dbc f clock = 165 msps; f out = 21 mhz 70 dbc f clock = 165 msps; f out = 41 mhz 60 dbc f clock = 210 msps; f out = 40 mhz 67 dbc f clock = 210 msps; f out = 69 mhz 63 dbc spurious-free dynamic range within a window f clock = 25 msps; f out = 1.00 mhz; 2 mhz span 80 dbc f clock = 50 msps; f out = 5.02 mhz; 2 mhz span 90 dbc f clock = 65 msps; f out = 5.03 mhz; 2.5 mhz span 90 dbc f clock = 125 msps; f out = 5.04 mhz; 4 mhz span 90 dbc total harmonic distortion f clock = 25 msps; f out = 1.00 mhz ?79 ?71 dbc f clock = 50 msps; f out = 2.00 mhz ?77 dbc f clock = 65 msps; f out = 2.00 mhz ?77 dbc f clock = 125 msps; f out = 2.00 mhz ?77 dbc signal-to-noise ratio f clock = 65 msps; f out = 5 mhz; i outfs = 20 ma 68 db f clock = 65 msps; f out = 5 mhz; i outfs = 5 ma 64 db f clock = 125 msps; f out = 5 mhz; i outfs = 20 ma 64 db f clock = 125 msps; f out = 5 mhz; i outfs = 5 ma 62 db f clock = 165 msps; f out = 5 mhz; i outfs = 20 ma 64 db f clock = 165 msps; f out = 5 mhz; i outfs = 5 ma 62 db f clock = 210 msps; f out = 5 mhz; i outfs = 20 ma 63 db f clock = 210 msps; f out = 5 mhz; i outfs = 5 ma 60 db
ad9740 rev. b | page 6 of 32 parameter min typ max unit multitone power ratio (8 tones at 400 khz spacing) f clock = 78 msps; f out = 15.0 mhz to 18.2 mhz 0 dbfs output 65 dbc ?6 dbfs output 66 dbc ?12 dbfs output 60 dbc ?18 dbfs output 55 dbc 1 measured single-ended into 50 load. 2 output noise is measured with a full-scale output set to 20 ma with no conversion activity. it is a measure of the thermal noi se only. 3 noise spectral density is the average nois e power normalized to a 1 hz bandwidth, with the dac converting and producing an out put tone. digital specifications t min to t max , avdd = 3.3 v, dvdd = 3.3 v, clkvdd = 3.3 v, i outfs = 20 ma, unless otherwise noted. table 3. parameter min typ max unit digital inputs 1 logic 1 voltage 2.1 3 v logic 0 voltage 0 0.9 v logic 1 current ?10 +10 a logic 0 current ?10 +10 a input capacitance 5 pf input setup time (t s ) 2.0 ns input hold time (t h ) 1.5 ns latch pulse width (t lpw ) 1.5 ns clk inputs 2 input voltage range 0 3 v common-mode voltage 0.75 1.5 2.25 v differential voltage 0.5 1.5 v 1 includes clock pin on soic/tssop packages and clk+ pin on lfcsp package in single-ended clock input mode. 2 applicable to clk+ and clk? inputs when conf igured for differential or pecl clock input mode. 0.1% 0.1% t s t h t pd db0?db9 clock iouta or ioutb t lpw t st 02911-002 figure 2. timing diagram
ad9740 rev. b | page 7 of 32 absolute maximum ratings table 4. parameter with respect to min max unit avdd acom ?0.3 +3.9 v dvdd dcom ?0.3 +3.9 v clkvdd clkcom ?0.3 +3.9 v acom dcom ?0.3 +0.3 v acom clkcom ?0.3 +0.3 v dcom clkcom ?0.3 +0.3 v avdd dvdd ?3.9 +3.9 v avdd clkvdd ?3.9 +3.9 v dvdd clkvdd ?3.9 +3.9 v clock, sleep dcom ?0.3 dvdd + 0.3 v digital inputs, mode dcom ?0.3 dvdd + 0.3 v iouta, ioutb acom ?1.0 avdd + 0.3 v refio, reflo, fs adj acom ?0.3 avdd + 0.3 v clk+, clk?, mode clkcom ?0.3 clkvdd + 0.3 v junction temperature 150 c storage temperature range ?65 +150 c lead temperature (10 sec) 300 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may effect device reliability. thermal characteristics 1 thermal resistance 28-lead 300-mil soic ja = 55.9c/w 28-lead tssop ja = 67.7c/w 32-lead lfcsp ja = 32.5c/w 1 thermal impedance measurements were taken on a 4-layer board in still air, in accordance with eia/jesd51-7. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd pr ecautions are recommended to avoid performance degradation or loss of functionality.
ad9740 rev. b | page 8 of 32 pin configurations and function descriptions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 nc = no connect 28 27 26 25 24 23 22 21 20 19 18 17 16 15 db8 db7 db6 db3 db4 db5 ( msb) db9 dvdd dcom mode iouta reserved avdd db2 db1 db0 nc nc nc ioutb acom nc sleep nc reflo refio fs adj clock ad9740 top view (not to scale) 02911-003 figure 3. 28-lead soic an d tssop pin configuration pin 1 indicator nc = no connect 1db3 2db2 3dvdd 4db1 5db0 6nc 7nc 8nc 24 fs adj 23 refio 22 acom 21 iouta 20 ioutb 19 acom 18 avdd 17 avdd 9 n c 1 0 d c o m 1 1 c l k v d d 1 2 c l k + 1 3 c l k ? 1 4 c l k c o m 1 5 c m o d e 1 6 m o d e 3 2 d b 4 3 1 d b 5 3 0 d b 6 2 9 d b 7 2 8 d b 8 2 7 d b 9 ( m s b ) 2 6 d c o m 2 5 s l e e p top view (not to scale) ad9740 02911-004 figure 4. 32-lead lfcsp pin configuration table 5. pin function descriptions soic/tssop pin no. lfcsp pin no. mnemonic description 1 27 db9 (msb) most significant data bit (msb). 2 to 9 28 to 32, 1, 2, 4 db8 to db1 data bits 8 to 1. 10 5 db0 (lsb) least significant data bit (lsb). 11 to 14, 19 6 to 9 nc no internal connection. 15 25 sleep power-down control input. active high. contai ns active pull-down circuit; it can be left unterminated if not used. 16 n/a reflo reference ground when internal 1.2 v reference used. connect to acom for both internal and external reference operation modes. 17 23 refio reference input/output. serves as referenc e input when using external reference. serves as 1.2 v reference output when using internal reference. requires 0.1 f capacitor to acom when using internal reference. 18 24 fs adj full-scale current output adjust. 20 19, 22 acom analog common. 21 20 ioutb complementary dac current output. full-scale current when all data bits are 0s. 22 21 iouta dac current output. full-scal e current when all data bits are 1s. 23 n/a reserved reserved. do not connect to common or supply. 24 17, 18 avdd analog supply voltage (3.3 v). 25 16 mode selects input data format. connect to dcom for straight binary, dvdd for twos complement. n/a 15 cmode clock mode selection. connect to clkcom for single-ended clock receiver (drive clk+ and float clkC). connect to clkvdd for differential receiver. float for pecl receiver (terminations on-chip). 26 10, 26 dcom digital common. 27 3 dvdd digital supply voltage (3.3 v). 28 n/a clock clock input. data latched on positive edge of clock. n/a 12 clk+ differential clock input. n/a 13 clk? differential clock input. n/a 11 clkvdd clock supply voltage (3.3 v). n/a 14 clkcom clock common.
ad9740 rev. b | page 9 of 32 terminology linearity error (also called integral nonlinearity or inl) linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. differential nonlinearity (or dnl) dnl is the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. monotonicity a dac is monotonic if the output either increases or remains constant as the digital input increases. offset error the deviation of the output current from the ideal of zero is called the offset error. for iouta, 0 ma output is expected when the inputs are all 0s. for ioutb, 0 ma output is expected when all inputs are set to 1s. gain error the difference between the actual and ideal output span. the actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. output compliance range the range of allowable voltage at the output of a current output dac. operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. temp er atu re d r i f t temperature drift is specified as the maximum change from the ambient (25c) value to the value at either t min or t max . for offset and gain drift, the drift is reported in ppm of full-scale range (fsr) per c. for reference drift, the drift is reported in ppm per c. power supply rejection the maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. settling time the time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. glitch impulse asymmetrical switching times in a dac give rise to undesired output transients that are quantified by a glitch impulse. it is specified as the net area of the glitch in pv-s. spurious-free dynamic range the difference, in db, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. t t otal harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. it is expressed as a percentage or in decibels (db). multitone power ratio the spurious-free dynamic range containing multiple carrier tones of equal amplitude. it is measured as the difference between the rms amplitude of a carrier tone to the peak spurious signal in the region of a removed tone. 150pf 1.2v ref avdd acom reflo pmos current source array segmented switches for db9?db1 lsb switches refio fs adj dvdd dcom clock 3.3v r set 2k 0.1 f dvdd dcom iouta ioutb ad9740 sleep 50 retimed clock output* latches digital data tektronix awg-2021 with option 4 lecroy 9210 pulse generator clock output 50 rohde & schwarz fsea30 spectrum analyzer mini-circuits t1-1t *awg2021 clock retimed so that the digital data transitions on falling edge of 50% duty cycle clock. 3.3v mode 50 figure 5. basic ac characterization test setup (soic/tssop packages)
ad9740 rev. b | page 10 of 32 typical performance characteristics f out (mhz) sfdr (dbc) 95 45 50 55 60 65 70 75 80 85 90 0 10 100 210msps 210msps (lfcsp) 02911-006 65msps 125msps 125msps (lfcsp) 165msps 165msps (lfcsp) figure 6. sfdr vs. f out @ 0 dbfs f out (mhz) sfdr (dbc) 95 45 50 55 60 65 70 75 80 85 90 0 5 10 15 20 25 ?12dbfs ?6dbfs 0dbfs 02911-007 figure 7. sfdr vs. f out @ 65 msps f out (mhz) sfdr (dbc) 95 45 50 55 60 65 70 75 80 85 90 01 0 52 0 15 3025 4035 45 0dbfs ?6dbfs ?12dbfs 02911-008 figure 8. sfdr vs. f out @ 125 msps f out (mhz) sfdr (dbc) 95 45 50 55 60 65 70 75 80 85 90 02 0 10 30 40 50 60 ?12dbfs ?6dbfs 0dbfs 02911-009 figure 9. sfdr vs. f out @ 165 msps f out (mhz) sfdr (dbc) 95 45 50 55 60 65 70 75 80 85 90 01 0 51 5 2 0 2 5 20ma 10ma 5ma 02911-010 figure 10. sfdr vs. f out and i outfs @ 65 msps and 0 dbfs f out (mhz) sfdr (dbc) 95 90 45 55 50 65 60 75 70 85 80 02 0 10 30 40 50 60 70 80 0dbfs (lfcsp) ?6dbfs (lfcsp) ?12dbfs (lfcsp) ?12dbfs ?6dbfs 0dbfs 02911-054 figure 11. sfdr vs. f out @ 210 msps
ad9740 rev. b | page 11 of 32 210msps (lfcsp) 210msps 02911-011 165msps 65msps a out (dbfs) sfdr (dbc) 95 90 45 55 50 65 60 75 70 85 80 ?25 ?15 ?20 ?10 ?5 0 125msps figure 12. single-tone sfdr vs. a out @ f out = f clock /11 a out (dbfs) sfdr (dbc) 95 45 55 65 75 85 90 50 60 70 80 ?25 ?15 ?20 ?10 ?5 0 210msps (lfcsp) 210msps 02911-012 165msps 125msps 65msps figure 13. single-tone sfdr vs. a out @ f out = f clock /5 f clock (msps) snr (db) 90 50 60 55 65 70 80 75 85 06 09 0 30 150 120 180 210 5ma 5ma (lfcsp) 10ma 20ma 10ma (lfcsp) 20ma (lfcsp) 02911-013 figure 14. snr vs. f clock and i outfs @ f out = 5 mhz and 0 dbfs a out (dbfs) sfdr (dbc) 95 45 55 65 75 85 ?25 ?15 ?20 ?10 ?5 0 210m sps (29, 31) lfcsp 210m sps (29, 31) 02911-014 78msps 165msps 125msps 65msps figure 15. dual-tone imd vs. a out @ f out = f clock /7 code error (lsb) 0.25 ?0.25 ?0.15 ?0.05 0.05 0.15 0 512 256 768 1024 02911-015 figure 16. typical inl code error (lsb) 0.25 ?0.25 ?0.15 ?0.05 0.05 0.15 0 512 256 768 1024 02911-016 figure 17. typical dnl
ad9740 rev. b | page 12 of 32 temperature ( c) sfdr (dbc) 90 80 85 50 55 60 70 65 75 ?40 0 20 ?20 40 60 80 4mhz 19mhz 34mhz 49mhz 02911-017 figure 18. sfdr vs. temperature @ 165 msps, 0 dbfs frequency (mhz) magnitude (dbm) 0 ?40 ?30 ?20 ?10 ?100 ?90 ?80 ?60 ?70 ?50 11 11 6 62 13 1 26 36 f clock = 78msps f out = 15.0mhz sfdr = 77dbc amplitude = 0dbfs 02911-018 figure 19. single-tone sfdr frequency (mhz) magnitude (dbm) 0 ?40 ?30 ?20 ?10 ?100 ?90 ?80 ?60 ?70 ?50 11 11 6 62 13 1 26 36 f clock = 78msps f out1 = 15.0mhz f out2 = 15.4mhz sfdr = 77dbc amplitude = 0dbfs 02911-019 figure 20. dual-tone sfdr frequency (mhz) magnitude (dbm) 0 ?40 ?30 ?20 ?10 ?100 ?90 ?80 ?60 ?70 ?50 11 11 6 62 13 1 26 36 f clock = 78msps f out1 = 15.0mhz f out2 = 15.4mhz f out3 = 15.8mhz f out4 = 16.2mhz sfdr = 72dbc amplitude = 0dbfs 02911-020 figure 21. four-tone sfdr digital data inputs (db9?db0) 150pf 1.2v ref avdd acom reflo pmos current source array 3.3v segmented switches for db9?db1 lsb switches refio fs adj dvdd dcom clock 3.3v r set 2k 0.1 f iouta ioutb ad9740 sleep latches i ref v refio clock ioutb iouta r load 50 v outb v outa r load 50 v diff = v outa ? v outb mode 02911-021 figure 22. simplified block diagram (soic/tssop packages)
ad9740 rev. b | page 13 of 32 functional description figure 22 shows a simplified block diagram of the ad9740. the ad9740 consists of a dac, digital control logic, and full-scale output current control. the dac contains a pmos current source array capable of providing up to 20 ma of full-scale current (i outfs ). the array is divided into 31 equal currents that make up the five most significant bits (msbs). the next four bits, or middle bits, consist of 15 equal current sources whose value is 1/16 of an msb current source. the remaining lsbs are binary weighted fractions of the middle bits current sources. implementing the middle and lower bits with current sources, instead of an r-2r ladder, enhances its dynamic performance for multitone or low amplitude signals and helps maintain the dacs high output impedance (that is, >100 k). all of these current sources are switched to one or the other of the two output nodes (that is, iouta or ioutb) via pmos differential current switches. the switches are based on the architecture that was pioneered in the ad9764 family, with further refinements to reduce distortion contributed by the switching transient. this switch architecture also reduces various timing errors and provides matching complementary drive signals to the inputs of the differential current switches. the analog and digital sections of the ad9740 have separate power supply inputs (that is, avdd and dvdd) that can operate independently over a 2.7 v to 3.6 v range. the digital section, which is capable of operating at a clock rate of up to 210 msps, consists of edge-triggered latches and segment decoding logic circuitry. the analog section includes the pmos current sources, the associated differential switches, a 1.2 v band gap voltage reference, and a reference control amplifier. the dac full-scale output current is regulated by the reference control amplifier and can be set from 2 ma to 20 ma via an external resistor, r set , connected to the full-scale adjust (fs adj) pin. the external resistor, in combination with both the reference control amplifier and voltage reference, v refio , sets the reference current, i ref , which is replicated to the segmented current sources with the proper scaling factor. the full-scale current, i outfs , is 32 times i ref . reference operation the ad9740 contains an internal 1.2 v band gap reference. the internal reference cannot be disabled, but can be easily overridden by an external reference with no effect on performance. figure 23 shows an equivalent circuit of the band gap reference. refio serves as either an output or an input depending on whether the internal or an external reference is used. to use the internal reference, simply decouple the refio pin to acom with a 0.1 f capacitor and connect reflo to acom via a resistance less than 5 . the internal reference voltage is present at refio. if the voltage at refio is to be used anywhere else in the circuit, then an external buffer amplifier with an input bias current of less than 100 na should be used. an example of the use of the internal reference is shown in figure 24 . a v dd 7k? 84a reflo refio 02911-057 figure 23. equivalent circuit of internal reference 150pf 1.2v ref avdd reflo current source array 3.3v refio fs adj 2k : 0.1 p f ad9740 a dditiona l load optional external ref buffer 02911-022 figure 24. internal reference configuration an external reference can be applied to refio, as shown in figure 25 . the external reference can provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. note that the 0.1 f compensation capacitor is not required because the internal reference is overridden, and the relatively high input impedance of refio minimizes any loading of the external reference.
ad9740 rev. b | page 14 of 32 150pf 1.2v ref avdd reflo current source array refio fs adj ad9740 reference control amplifier 3.3 v 02911-023 figure 25. external reference configuration reference control amplifier the ad9740 contains a control amplifier that is used to regulate the full-scale output current, i outfs . the control amplifier is configured as a v-i converter, as shown in figure 24 , so that its current output, i ref , is determined by the ratio of the v refio and an external resistor, r set , as stated in equation 4. i ref is copied to the segmented current sources with the proper scale factor to set i outfs , as stated in equation 3. the control amplifier allows a wide (10:1) adjustment span of i outfs over a 2 ma to 20 ma range by setting i ref between 62.5 a and 625 a. the wide adjustment span of i outfs provides several benefits. the first relates directly to the power dissipation of the ad9740, which is proportional to i outfs (see the power dissipation section). the second relates to a 20 db adjustment, which is useful for system gain control purposes. the small signal bandwidth of the reference control amplifier is approximately 500 khz and can be used for low frequency small signal multiplying applications. dac transfer function the ad9740 provides complementary current outputs, iouta and ioutb. iouta provides a near full-scale current output, i outfs , when all bits are high (that is, dac code = 1023), while ioutb, the complementary output, provides no current. the current output appearing at iouta and ioutb is a function of both the input code and i outfs and can be expressed as: iouta = ( dac code/1023) i outfs (1) ioutb = (1023 ? dac code )/1024 i outfs (2) where dac code = 0 to 1023 (that is, decimal representation). as mentioned previously, i outfs is a function of the reference current i ref , which is nominally set by a reference voltage, v refio , and external resistor, r set . it can be expressed as: i outfs = 32 i ref (3) where i ref = v refio / r set (4) the two current outputs typically drive a resistive load directly or via a transformer. if dc coupling is required, then iouta and ioutb should be directly connected to matching resistive loads, r load , that are tied to analog common, acom. note that r load can represent the equivalent load resistance seen by iouta or ioutb, as would be the case in a doubly terminated 50 or 75 cable. the single-ended voltage output appearing at the iouta and ioutb nodes is simply v outa = iouta r load (5) v outb = ioutb r load (6) note that the full-scale value of v outa and v outb should not exceed the specified output compliance range to maintain specified distortion and linearity performance. v diff = ( iouta ? ioutb ) r load (7) substituting the values of iouta , iout b, i ref , and v diff can be expressed as: v diff = {(2 dac code ? 1023)/1024} (32 r load / r set ) v refio (8) equation 7 and equation 8 highlight some of the advantages of operating the ad9740 differentially. first, the differential operation helps cancel common-mode error sources associated with iouta and ioutb, such as noise, distortion, and dc offsets. second, the differential code-dependent current and subsequent voltage, v diff , is twice the value of the single-ended voltage output (that is, v outa or v outb ), thus providing twice the signal power to the load. note that the gain drift temperature performance for a single- ended (v outa and v outb ) or differential output (v b diff ) of the ad9740 can be enhanced by selecting temperature tracking resistors for r load and r set due to their ratiometric relationship, as shown in equation 8. analog outputs the complementary current outputs in each dac, iouta, and ioutb can be configured for single-ended or differential operation. iouta and ioutb can be converted into complementary single-ended voltage outputs, v outa and v outb , via a load resistor, r load , as described in the dac transfer function section by equation 5 through equation 8. the differential voltage, v diff , existing between v outa and v outb , can also be converted to a single-ended voltage via a transformer or differential amplifier configuration. the ac performance of the ad9740 is optimum and specified using a differential transformer-coupled output in which the voltage swing at iouta and ioutb is limited to 0.5 v. the distortion and noise performance of the ad9740 can be enhanced when it is configured for differential operation. the common-mode error sources of both iouta and ioutb can be significantly reduced by the common-mode rejection of a
ad9740 rev. b | page 15 of 32 transformer or differential amplifier. these common-mode error sources include even-order distortion products and noise. the enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases and/or its amplitude decreases. this is due to the first-order cancellation of various dynamic common- mode distortion mechanisms, digital feedthrough, and noise. performing a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the reconstructed signal power to the load (assuming no source termination). because the output currents of iouta and ioutb are complementary, they become additive when processed differentially. a properly selected transformer allows the ad9740 to provide the required power and voltage levels to different loads. the output impedance of iouta and ioutb is determined by the equivalent parallel combination of the pmos switches associated with the current sources and is typically 100 k in parallel with 5 pf. it is also slightly dependent on the output voltage (that is, v outa and v outb ) due to the nature of a pmos device. as a result, maintaining iouta and/or ioutb at a virtual ground via an i-v op amp configuration results in the optimum dc linearity. note that the inl/dnl specifications for the ad9740 are measured with iouta maintained at a virtual ground via an op amp. iouta and ioutb also have a negative and positive voltage compliance range that must be adhered to in order to achieve optimum performance. the negative output compliance range of ?1 v is set by the breakdown limits of the cmos process. operation beyond this maximum limit can result in a breakdown of the output stage and affect the reliability of the ad9740. the positive output compliance range is slightly dependent on the full-scale output current, i outfs . it degrades slightly from its nominal 1.2 v for an i outfs = 20 ma to 1 v for an i outfs = 2 ma. the optimum distortion performance for a single-ended or differential output is achieved when the maximum full-scale signal at iouta and ioutb does not exceed 0.5 v. digital inputs the ad9740 digital section consists of 10 input bit channels and a clock input. the 10-bit parallel data inputs follow standard positive binary coding, where db9 is the most significant bit (msb) and db0 is the least significant bit (lsb). iouta produces a full-scale output current when all data bits are at logic 1. ioutb produces a complementary output with the full-scale current split between the two outputs as a function of the input code. dvdd digital input 02911-024 figure 26. equivalent digital input the digital interface is implemented using an edge-triggered master/slave latch. the dac output updates on the rising edge of the clock and is designed to support a clock rate as high as 210 msps. the clock can be operated at any duty cycle that meets the specified latch pulse width. the setup and hold times can also be varied within the clock cycle as long as the specified minimum times are met, although the location of these transition edges can affect digital feedthrough and distortion performance. best performance is typically achieved when the input data transitions on the falling edge of a 50% duty cycle clock. clock input soic/tssop packages the 28-lead package options have a single-ended clock input (clock) that must be driven to rail-to-rail cmos levels. the quality of the dac output is directly related to the clock quality, and jitter is a key concern. any noise or jitter in the clock translates directly into the dac output. optimal performance is achieved if the clock input has a sharp rising edge, because the dac latches are positive edge triggered. lfcsp package a configurable clock input is available in the lfcsp package, which allows for one single-ended and two differential modes. the mode selection is controlled by the cmode input, as summarized in table 6 . connecting cmode to clkcom selects the single-ended clock input. in this mode, the clk+ input is driven with rail-to-rail swings and the clk? input is left floating. if cmode is connected to clkvdd, then the differential receiver mode is selected. in this mode, both inputs are high impedance. the final mode is selected by floating cmode. this mode is also differential, but internal terminations for positive emitter-coupled logic (pecl) are activated. there is no significant performance difference between any of the three clock input modes. table 6. clock mode selection cmode pin clock input mode clkcom single-ended clkvdd differential float pecl the single-ended input mode operates in the same way as the clock input in the 28-lead packages, as described previously.
ad9740 rev. b | page 16 of 32 in the differential input mode, the clock input functions as a high impedance differential pair. the common-mode level of the clk+ and clk? inputs can vary from 0.75 v to 2.25 v, and the differential voltage can be as low as 0.5 v p-p. this mode can be used to drive the clock with a differential sine wave because the high gain bandwidth of the differential inputs converts the sine wave into a single-ended square wave internally. the final clock mode allows for a reduced external component count when the dac clock is distributed on the board using pecl logic. the internal termination configuration is shown in figure 27 . these termination resistors are untrimmed and can vary up to 20%. however, matching between the resistors should generally be better than 1%. clk+ to dac core clk? v tt = 1.3v nom 50 50 ad9740 clock receiver 02911-025 figure 27. clock termination in pecl mode dac timing input clock and data timing relationship dynamic performance in a dac is dependent on the relationship between the position of the clock edges and the time at which the input data changes. the ad9740 is rising edge triggered, and so exhibits dynamic performance sensitivity when the data transition is close to this edge. in general, the goal when applying the ad9740 is to make the data transition close to the falling clock edge. this becomes more important as the sample rate increases. figure 28 shows the relationship of sfdr to clock placement with different sample rates. note that at the lower sample rates, more tolerance is allowed in clock placement, while at higher rates, more care must be taken. ?3 ?2 2 ?1 0 1 65 75 ns db 3 55 45 35 60 70 50 40 50mhz sfdr 20mhz sfdr 50mhz sfdr 02911-026 figure 28. sfdr vs. clock placement @ f out = 20 mhz and 50 mhz (f clock = 165 msps) sleep mode operation the ad9740 has a power-down function that turns off the output current and reduces the supply current to less than 6 ma over the specified supply range of 2.7 v to 3.6 v and the temperature range. this mode can be activated by applying a logic level 1 to the sleep pin. the sleep pin logic threshold is equal to 0.5 avdd. this digital input also contains an active pull-down circuit that ensures that the ad9740 remains enabled if this input is left disconnected. the ad9740 takes less than 50 ns to power down and approximately 5 s to power back up. power dissipation the power dissipation, p d , of the ad9740 is dependent on several factors that include: ? the power supply voltages (avdd, clkvdd, and dvdd) ? the full-scale current output (i outfs ) ? the update rate (f clock ) ? the reconstructed digital input waveform the power dissipation is directly proportional to the analog supply current, i avdd , and the digital supply current, i dvdd . i avdd is directly proportional to i outfs , as shown in figure 29 , and is insensitive to f clock . conversely, i dvdd is dependent on both the digital input waveform, f clock , and digital supply dvdd. figure 30 shows i dvdd as a function of full-scale sine wave output ratios (f out /f clock ) for various update rates with dvdd = 3.3 v.
ad9740 rev. b | page 17 of 32 i outfs (ma) 35 0 2 i avdd (ma) 30 25 20 15 10 4 6 8 101214161820 02911-027 figure 29. i avdd vs. i outfs ratio (f out /f clock ) 20 0.01 1 0.1 i dvdd (ma) 14 16 18 12 10 8 6 4 2 0 165msps 210msps 65msps 02911-055 125msps figure 30. i dvdd vs. ratio @ dvdd = 3.3 v f clock (msps) i clkvdd (ma) 11 0 0 150 100 50 200 250 pecl diff se 10 9 8 7 6 5 4 3 2 1 02911-056 figure 31. i clkvdd vs. f clock and clock mode applying the ad9740 output configurations the following sections illustrate some typical output configurations for the ad9740. unless otherwise noted, it is assumed that i outfs is set to a nominal 20 ma. for applications requiring the optimum dynamic performance, a differential output configuration is suggested. a differential output configuration can consist of either an rf transformer or a differential op amp configuration. the transformer configuration provides the optimum high frequency performance and is recommended for any application that allows ac coupling. the differential op amp configuration is suitable for applications requiring dc coupling, bipolar output, signal gain, and/or level shifting within the bandwidth of the chosen op amp. a single-ended output is suitable for applications requiring a unipolar voltage output. a positive unipolar output voltage results if iouta and/or ioutb is connected to an appropriately sized load resistor, r load , referred to acom. this configuration can be more suitable for a single-supply system requiring a dc-coupled, ground referred output voltage. alternatively, an amplifier could be configured as an i-v converter, thus converting iouta or ioutb into a negative unipolar voltage. this configuration provides the best dc linearity because iouta or ioutb is maintained at a virtual ground. differential coupling using a transformer an rf transformer can be used to perform a differential-to- single-ended signal conversion, as shown in figure 32 . a differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformers pass band. an rf transformer, such as the mini-circuits? t1C1t, provides excellent rejection of common-mode distortion (that is, even- order harmonics) and noise over a wide frequency range. it also provides electrical isolation and the ability to deliver twice the power to the load. transformers with different impedance ratios can also be used for impedance matching purposes. note that the transformer provides ac coupling only. r load ad9740 mini-circuits t1-1t optional r diff iouta ioutb 22 21 02911-030 figure 32. differential output using a transformer
ad9740 rev. b | page 18 of 32 the center tap on the primary side of the transformer must be connected to acom to provide the necessary dc current path for both iouta and ioutb. the complementary voltages appearing at iouta and ioutb (that is, v outa and v outb ) swing symmetrically around acom and should be maintained with the specified output compliance range of the ad9740. a differential resistor, r b diff , can be inserted in applications where the output of the transformer is connected to the load, r load , via a passive reconstruction filter or cable. r diff is determined by the transformers impedance ratio and provides the proper source termination that results in a low vswr. note that approximately half the signal power is dissipated across r diff . differential coupling using an op amp an op amp can also be used to perform a differential-to-single- ended conversion, as shown in figure 33 . the ad9740 is configured with two equal load resistors, r load , of 25 . the differential voltage developed across iouta and ioutb is converted to a single-ended signal via the differential op amp configuration. an optional capacitor can be installed across iouta and ioutb, forming a real pole in a low-pass filter. the addition of this capacitor also enhances the op amps distortion performance by preventing the dacs high slewing output from overloading the op amps input. ad9740 iouta ioutb c opt 500 225 225 500 25 25 ad8047 22 21 02911-031 figure 33. dc differential coupling using an op amp the common-mode rejection of this configuration is typically determined by the resistor matching. in this circuit, the differential op amp circuit using the ad8047 is configured to provide some additional signal gain. the op amp must operate off a dual supply because its output is approximately 1 v. a high speed amplifier capable of preserving the differential performance of the ad9740 while meeting other system level objectives (that is, cost or power) should be selected. the op amps differential gain, gain setting resistor values, and full-scale output swing capabilities should all be considered when optimizing this circuit. the differential circuit shown in figure 34 provides the necessary level shifting required in a single-supply system. in this case, avdd, which is the positive analog supply for both the ad9740 and the op amp, is also used to level shift the differential output of the ad9740 to midsupply (that is, avdd/2). the ad8041 is a suitable op amp for this application. ad9740 iouta ioutb c opt 500 225 225 1k 25 25 ad8041 1k avdd 22 21 02911-032 figure 34. single-supply dc differential coupled circuit single-ended, unbuffered voltage output figure 35 shows the ad9740 configured to provide a unipolar output range of approximately 0 v to 0.5 v for a doubly terminated 50 cable because the nominal full-scale current, i outfs , of 20 ma flows through the equivalent r load of 25 . in this case, r load represents the equivalent load resistance seen by iouta or ioutb. the unused output (iouta or ioutb) can be connected to acom directly or via a matching r load . different values of i outfs and r load can be selected as long as the positive compliance range is adhered to. one additional consideration in this mode is the integral nonlinearity (inl), discussed in the analog outputs section. for optimum inl performance, the single-ended, buffered voltage output configuration is suggested. ad9740 iouta ioutb 50 25 v outa = 0v to 0.5v i outfs = 20ma 50 22 21 02911-033 figure 35. 0 v to 0.5 v unbuffered voltage output single-ended, buffered voltage output configuration figure 36 shows a buffered single-ended output configuration in which the op amp u1 performs an i-v conversion on the ad9740 output current. u1 maintains iouta (or ioutb) at a virtual ground, minimizing the nonlinear output impedance effect on the dacs inl performance as described in the analog outputs section. although this single-ended configuration typically provides the best dc linearity performance, its ac distortion performance at higher dac update rates can be limited by u1s slew rate capabilities. u1 provides a negative unipolar output voltage, and its full-scale output voltage is simply the product of r fb and i outfs . the full-scale output should be set within u1s voltage output swing capabilities by scaling i outfs and/or r fb . an improvement in ac distortion performance can result with a reduced i outfs because u1 is required to sink less signal current.
ad9740 rev. b | page 19 of 32 ad9740 iouta ioutb c opt 200 u1 v out = i outfs r fb i outfs = 10ma r fb 200 22 21 02911-034 figure 36. unipolar buffered voltage output power and grounding considerations, power supply rejection many applications seek high speed and high performance under less than ideal operating conditions. in these application circuits, the implementation and construction of the printed circuit board is as important as the circuit design. proper rf techniques must be used for device selection, placement, and routing as well as power supply bypassing and grounding to ensure optimum performance. figure 41 to figure 44 illustrate the recommended printed circuit board ground, power, and signal plane layouts implemented on the ad9740 evaluation board. one factor that can measurably affect system performance is the ability of the dac output to reject dc variations or ac noise superimposed on the analog or digital dc power distribution. this is referred to as the power supply rejection ratio (psrr). for dc variations of the power supply, the resulting performance of the dac directly corresponds to a gain error associated with the dacs full-scale current, i outfs . ac noise on the dc supplies is common in applications where the power distribution is generated by a switching power supply. typically, switching power supply noise occurs over the spectrum from tens of kilohertz to several megahertz. the psrr vs. frequency of the ad9740 avdd supply over this frequency range is shown in figure 37 . frequency (mhz) 85 40 12 6810 0 psrr (db) 80 75 70 65 60 55 50 24 45 02911-035 figure 37. power supply rejection ratio (psrr) note that the ratio in figure 37 is calculated as amps out/volts in. noise on the analog power supply has the effect of modulating the internal switches, and therefore the output current. the voltage noise on avdd, therefore, is added in a nonlinear manner to the desired iout. due to the relative different size of these switches, the psrr is very code dependent. this can produce a mixing effect that can modulate low frequency power supply noise to higher frequencies. worst-case psrr for either one of the differential dac outputs occur when the full-scale current is directed toward that output. as a result, the psrr measurement in figure 37 represents a worst-case condition in which the digital inputs remain static and the full-scale output current of 20 ma is directed to the dac output being measured. the following illustrates the effect of supply noise on the analog supply. suppose a switching regulator with a switching frequency of 250 khz produces 10 mv of noise and, for simplicitys sake (ignoring harmonics), all of this noise is concentrated at 250 khz. to calculate how much of this undesired noise appears as current noise superimposed on the dacs full-scale current, i outfs , users must determine the psrr in db using figure 37 at 250 khz. to calculate the psrr for a given r load , such that the units of psrr are converted from a/v to v/v, adjust the curve in figure 37 by the scaling factor 20 log (r load ). for instance, if r load is 50 , then the psrr is reduced by 34 db (that is, psrr of the dac at 250 khz, which is 85 db in figure 37 , becomes 51 db v out /v in ). proper grounding and decoupling should be a primary objective in any high speed, high resolution system. the ad9740 features separate analog and digital supplies and ground pins to optimize the management of analog and digital ground currents in a system. in general, avdd, the analog supply, should be decoupled to acom, the analog common, as close to the chip as physically possible. similarly, dvdd, the digital supply, should be decoupled to dcom as close to the chip as physically possible. for those applications that require a single 3.3 v supply for both the analog and digital supplies, a clean analog supply can be generated using the circuit shown in figure 38 . the circuit consists of a differential lc filter with separate power supply and return lines. lower noise can be attained by using low esr type electrolytic and tantalum capacitors. 100 f elect. 0.1 f cer. ttl/cmos logic circuits 3.3v power supply ferrite beads avdd acom 10 f?22 f tant. 02911-036 figure 38. differential lc filter for single 3.3 v applications
ad9740 rev. b | page 20 of 32 evaluation board general description the txdac family evaluation boards allow for easy setup and testing of any txdac product in the soic and lfcsp packages. careful attention to layout and circuit design, combined with a prototyping area, allows the user to evaluate the ad9740 easily and effectively in any application where high resolution, high speed conversion is required. this board allows the user the flexibility to operate the ad9740 in various configurations. possible output configurations include transformer coupled, resistor terminated, and single and differential outputs. the digital inputs are designed to be driven from various word generators, with the on-board option to add a resistor network for proper load termination. provisions are also made to operate the ad9740 with either the internal or external reference or to exercise the power-down feature. 2 r1 3 r2 4 r3 5 r4 6 r5 7 r6 8 r7 9 r8 10 r9 rp5 opt 1 dcom 16 1 rp3 22 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db13x db12x db11x db10x db9x db8x db7x db6x db5x db4x db3x db2x db1x db0x 15 2 rp3 22 14 3 rp3 22 13 4 rp3 22 12 5 rp3 22 11 6 rp3 22 10 7 rp3 22 9 8 rp3 22 16 1 rp4 22 15 2 rp4 22 14 3 rp4 22 13 4 rp4 22 12 5 rp4 22 11 6 rp4 22 9 8 rp4 22 10 7 rp4 22 ckext ckextx 2 r1 3 r2 4 r3 5 r4 6 r5 7 r6 8 r7 9 r8 10 r9 rp6 opt 1 dcom 2 r1 3 r2 4 r3 5 r4 6 r5 7 r6 8 r7 9 r8 10 r9 rp1 opt 1 dcom 2 r1 3 r 2 4 r3 5 r4 6 r5 7 r6 8 r7 9 r8 10 r9 rp2 opt 1 dcom 21 db13x 4 3 db12x 65 db11x 87 db10x 10 9 db9x 12 11 db8x 14 13 db7x 16 15 db6x 18 17 db5x 20 19 db4x 22 21 db3x 24 23 db2x 26 25 db1x 28 27 db0x 30 29 32 31 34 33 ckextx 36 35 38 37 40 39 jp3 j1 ribbon tb1 1 tb1 2 l2 bead c7 0.1 f tp4 blk + dvdd tp7 c6 0.1 f c4 10 f 25v blk blk tp8 tp2 red tb1 3 tb1 4 l3 bead c9 0.1 f tp6 blk + avdd tp10 c8 0.1 f c5 10 f 25v blk blk tp9 tp5 red 02911-037 figure 39. soic evaluation boar dpower supply and digital inputs
ad9740 rev. b | page 21 of 32 r6 opt s2 iouta 2 a b jp10 1 3 ix c13 opt jp8 iout s3 4 5 6 3 2 1 t1 t1-1t jp9 c12 opt r10 10k s1 ioutb 1 2 3 ab jp11 iy 1 ext 2 3 int ab jp5 ref + + c14 16v a v dd dvdd c kext db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 avdd c15 16v cut under dut jp6 jp4 r5 opt dvdd r4 clock s5 clock tp1 wht dvdd avdd dvdd r2 jp2 mode tp3 wht ref c2 c1 c11 r1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 u1 ad9740 sleep tp11 wht r3 clock dvdd dcom mode avdd reserved iouta ioutb acom nc fs adj refio reflo sleep db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 avdd 02911-038 c17 0.1 f c16 0.1 f 10 f 10 f c19 0.1 f c18 0.1 f 0.1 f 2k 10k 0.1 f 0.1 f r11 10k 10k 50 figure 40. soic evaluation boar doutput signal conditioning
ad9740 rev. b | page 22 of 32 02911-039 figure 41. soic evaluation boardprimary side 02911-040 figure 42. soic evaluation boardsecondary side
ad9740 rev. b | page 23 of 32 02911-041 figure 43. soic evaluation boardground plane 02911-042 figure 44. soic evaluation boardpower plane
ad9740 rev. b | page 24 of 32 02911-043 figure 45. soic evaluation board assemblyprimary side 02911-044 figure 46. soic evaluation board assemblysecondary side
ad9740 rev. b | page 25 of 32 cvdd red tp12 bead tb1 1 tb1 2 c7 0.1 f c9 0.1 f c3 0.1 f blk tp2 tp4 tp6 blk blk c6 0.1 f c8 0.1 f c10 0.1 f c2 10 f 6.3v c4 10 f 6.3v c5 10 f 6.3v l1 dvdd red tp13 bead tb3 1 tb3 2 l2 avdd red tp5 bead tb4 1 tb4 2 l3 j1 13 11 9 7 5 3 1 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 39 37 35 33 31 29 27 25 23 21 19 17 15 header straight up male no shroud jp3 ckextx ckext ckextx r21 100 r24 100 r25 100 r26 100 r27 100 r28 100 db0x db1x db2x db3x db4x db5x db6x db7x db8x db9x db10x db11x db12x db13x db0x db1x db2x db3x db4x db5x db6x db7x db8x db9x db10x db11x db12x db13x db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 22 16 22 15 22 14 22 13 22 12 22 11 22 10 22 9 22 16 22 15 22 14 22 13 22 12 22 11 22 10 22 9 r20 100 r19 100 r18 100 r17 100 r16 100 r15 100 r4 100 r3 100 1 rp3 2 rp3 3 rp3 4 rp3 5 rp3 6 rp3 7 rp3 8 rp3 1 rp4 2 rp4 3 rp4 4 rp4 5 rp4 6 rp4 7 rp4 8 rp4 02911-045 figure 47. lfcsp evaluation board schematicpower supply and digital inputs
ad9740 rev. b | page 26 of 32 c19 cvdd cvdd db8 db9 db10 db11 clkb db5 dvdd db6 db7 clk db0 db1 db2 db3 db4 db13 db12 iout avdd dvdd cvdd a v dd db8 db9 db10 db11 ib fs adj clkb db5 dvdd db6 db7 clk cvdd dcom db0 db1 db2 db3 db4 dcom1 db13 acom1 avdd acom ia refio avdd1 sleep db12 ccom cmode mode cmode mode t1 ? 1t t1 jp8 jp9 4 3 2 1 5 6 agnd: 3, 4, 5 s3 r11 c13 28 25 17 23 21 22 18 19 27 26 24 20 29 30 31 32 dnp dnp c12 c11 c17 c19 c32 r30 r29 u1 ad9740lfcsp 14 5 6 7 8 9 10 11 12 1 2 3 4 13 15 16 wht tp1 wht tp11 jp1 0.1% r1 r10 wht tp3 tp7 wht sleep 02911-046 10k 10k 50k 50 2k 0.1 f 0.1 f 0.1 f 0.1 f figure 48. lfcsp evaluation board schematicoutput signal conditioning u4 u4 jp2 agnd: 5 cvdd: 8 4 3 6 cvdd: 8 c35 0.1 f c20 10 f 16v s5 agnd: 3, 4, 5 c34 0.1 f ckext clk clkb r5 120 r2 120 r6 50 cvdd agnd: 5 2 1 7 cvdd 02911-047 figure 49. lfcsp evaluation board schematicclock input
ad9740 rev. b | page 27 of 32 02911-048 figure 50. lfcsp evaluation board layoutprimary side 02911-049 figure 51. lfcsp evaluation board layoutsecondary side
ad9740 rev. b | page 28 of 32 02911-050 figure 52. lfcsp evaluation board layoutground plane 02911-051 figure 53. lfcsp evaluation board layoutpower plane
ad9740 rev. b | page 29 of 32 02911-052 figure 54. lfcsp evaluation board layout assemblyprimary side 02911-053 figure 55. lfcsp evaluation board layout assemblysecondary side
ad9740 rev. b | page 30 of 32 outline dimensions compliant to jedec standards mo-153-ae 28 15 14 1 8 0 seating plane c oplanarit y 0.10 1.20 max 6.40 bsc 0.65 bsc pin 1 0.30 0.19 0.20 0.09 4.50 4.40 4.30 0.75 0.60 0.45 9.80 9.70 9.60 0.15 0.05 figure 56. 28-lead thin shrink small outline package [tssop] (ru-28) dimensions shown in millimeters controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013-ae 0.33 (0.0130) 0.20 (0.0079) 8 0 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) seating plane 0.30 (0.0118) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) bsc 28 15 14 1 18.10 (0.7126) 17.70 (0.6969) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) coplanarity 0.10 figure 57. 28-lead standard small outline package [soic] wide body (rw-28) dimensions shown in millimeters and (inches)
ad9740 rev. b | page 31 of 32 compliant to jedec standards mo-220-vhhd-2 0.30 0.23 0.18 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 12 max 1.00 0.85 0.80 seating plane coplanarity 0.08 1 32 8 9 25 24 16 17 0.50 0.40 0.30 3.50 ref 0.50 bsc pin 1 indicator top view 5.00 bsc sq 4.75 bsc sq 3.25 3.10 sq 2.95 pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bottom view) figure 58. 32-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-32-2) dimensions shown in millimeters ordering guide model temperature range package description package option ad9740ar ?40c to +85c 28-lead wide body soic rw-28 ad9740arrl ?40c to +85c 28-le ad wide body soic rw-28 ad9740arz 1 ?40c to +85c 28-lead wide body soic rw-28 ad9740arzrl 1 ?40c to +85c 28-lead wide body soic rw-28 ad9740aru ?40c to +85c 28-lead tssop ru-28 ad9740arurl7 ?40c to +85c 28-lead tssop ru-28 ad9740aruz 1 ?40c to +85c 28-lead tssop ru-28 ad9740aruzrl7 1 ?40c to +85c 28-lead tssop ru-28 ad9740acp ?40c to +85c 32-lead lfcsp cp-32-2 AD9740ACPRL7 ?40c to +85c 32-lead lfcsp_vq cp-32-2 ad9740acpz 1 ?40c to +85c 32-lead lfcsp_vq cp-32-2 ad9740acpzrl7 1 ?40c to +85c 32-lead lfcsp_vq cp-32-2 ad9740-eb evaluation board (soic) ad9740acp-pcb evaluation board (lfcsp) 1 z = pb-free part.
ad9740 rev. b | page 32 of 32 notes ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c02911C0C12/05(b)

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